Radios, wireless devices, and other high frequency applications often require several sources of ultra-high frequency (UHF), very-high frequency (VHF), radio frequency (RF) or other high frequency signals. Programmable dividers can be utilized to generate frequency signals at various frequencies. The programmable divider or programmable prescaler typically receives a divisor at a selection input and an input signal at a clock input. The divider provides an output signal (generally a square wave) which has a frequency equal to the frequency of the input signal divided by the divisor.
Heretofore, programmable dividers have produced output signals which have variable duty cycles (e.g., the ratio of on-time to off-time). The variable duty cycle is often a function of the divisor provided at the selection input. For example, U.S. Pat. No. 4,575,867 discloses a programmable divider or prescaler which can divide the frequency of an input signal by a factor of (2.sup.m +n), where m is an integer and n is a whole number from zero to (2.sup.m -1). The divider can provide output signals having a duty cycle approaching 50% for some values of the divisor. However when other values are utilized, duty cycles more than 33% away from 50% are produced (e.g., for m=3 and n=7, 4 positive pulses and 11 negative pulses results in a duty cycle of 4/15 or 26%).
When a programmable divider is utilized to provide an injection signal to balanced mixers, mixer performance is degraded if the duty cycle is significantly greater than or less than 50%. A mixer has improved spurious performance when provided with a signal having a duty cycle close to 50%.
Thus, there is a need for a programmable divider or prescaler which can provide a duty cycle that approaches 50% for all values of its divisor. Further still, there is a need for a programmable divider which can divide the frequency of a signal by a significant number of divisors and yet provide a duty cycle approaching 50% for all values of the divisors. Even further still, there is a need for a programmable divider which provides an output signal having an approximately 50% duty cycle which is not limited by critical path delays.